The present invention is directed to a dynamic memory refresh controller and method for prioritizing the refresh requests issued to the memory based on the number of pending refresh requests to the memory. More particularly, the refresh controller and method determine the number of refresh requests that are pending to the memory and issue the refresh requests to the memory as either a high priority request or a low priority request in response to the comparison of the number of pending refresh requests to a predetermined refresh number.
In conventional dynamic memories, the time that a node reliably stores a bit is referred to as the refresh period. The refresh period is based on the particular dynamic memory specifications. Since the charge stored on a dynamic node decays, it is necessary to sense and refresh the dynamic node within the refresh period. Therefore, dynamic memories are generally interfaced to a refresh circuit which generates a refresh request within the refresh period to ensure that the charge on the dynamic node does not decay and the bit remains reliably stored on the dynamic node.
An example of a known refresh operation for a dynamic memory system is illustrated in FIG. 1. A refresh circuit 10 generates refresh requests at predetermined intervals to the memory controller 20. The predetermined intervals are chosen to be within the refresh period to ensure that data on the dynamic node reliably remains. Conventionally, the predetermined intervals are about 15 .mu.sec. More specifically, the refresh circuit 10 generates an overflow signal at the end of the predetermined intervals. The generated overflow signals act as refresh requests which take priority before all of the other requests from an external processor (not shown). In these known systems, because the refresh requests take priority of the execution by the memory controller 20 before all of the other requests, the read latency is adversely affected due to the refreshes. For example, in the middle of a large block transfer, a read which conflicts with the refresh will be forced to wait until the refresh, which takes priority, is completed. The amount of time necessary to complete the refresh is dependent upon the number of banks in the dynamic memory and thereby, the read latency becomes higher as the number of banks is increased.
A refresh controller for a memory is therefore desired which minimizes the read latency caused by refreshes while guaranteeing refresh requests to be executed to the memory within the refresh period. The embodiments of the present invention are directed to solving the above-described refresh concerns in known dynamic memory systems so that refreshes will occur within the refresh period while keeping the read latency low.